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Konferenzbeiträge
Zeitschriften
Buchkapitel
Bücher
Workshop Beiträge
Report
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Konferenzbeiträge

  • Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test
    2017 M. Kampmann, S. Hellebrand
    20th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Dresden, Germany
  • X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
    2016 S. Hellebrand, M. Kampmann
    Proceedings of 25th IEEE Asian Test Symposium (ATS), Hiroshima, Japan. November 2016, pp 1-6
  • Optimized Selection of Frequencies for Faster-than-at-Speed Test
    2015 M. Kampmann, M. Kochte, E. Scheider, T. Indlekofer, S. Hellebrand, H. Wunderlich
    Proceedings Asian Test Symposium, Mumbai, India, Nov. 2015
  • FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
    2014 S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'14), Seattle, Washington USA, October 21-23, 2014
  • Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
    2012 A. Cook, S. Hellebrand, H. Wunderlich
    Proceedings IEEE European Test Symposium, Annecy, France, May 2012, pp. 1-6
  • Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
    2012 A. Cook, S. Hellebrand, M. Imhof, A. Mumtaz, H. Wunderlich
    Proceedings Latin American Test Workshop, Quito, Ecuador, April 2012, pp. 1-4
  • Diagnostic Test of Robust Circuits
    2011 A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich
    Proceedings 20th Asian Test Symposium, New Delhi, India, November, 2011, pp. 285-290
  • Robuster Selbsttest mit Diagnose
    2011 A. Cook, S. Hellebrand, T. Indlekofer, H. Wunderlich
    5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf", Hamburg, September 2011, pp. 48-53
  • Towards Variation-Aware Test Methods
    2011 I. Polian, B. Becker, S. Hellebrand, H. Wunderlich, P. Maxwell
    Proceedings 16th IEEE European Test Symposium, Trondheim, Norway, May 2011 (Embedded Tutorial)
  • Variation-Aware Fault Modeling
    2010 F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    Proceedings 19th Asian Test Symposium, Shanghai, China, December 1-4, 2010, pp. 87-93
  • The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
    2010 M. Hunger, S. Hellebrand
    Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), Kyoto, Japan, October 2010, pp. 101-108
  • Efficient Test Response Compaction for Robust BIST Using Parity Sequences
    2010 T. Indlekofer, M. Schnittger, S. Hellebrand
    Proceedings 28th IEEE International Conference on Computer Design (ICCD'10), Amsterdam, The Netherlands, October 2010, pp. 480-485
  • Robuster Selbsttest mit extremer Kompaktierung
    2010 T. Indlekofer, M. Schnittger, S. Hellebrand
    4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 17-24
  • Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
    2010 M. Hunger, S. Hellebrand
    4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Wildbad Kreuth, September 2010, pp. 81-88
  • Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
    2010 B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), Chicago, IL, USA, June 2010 (Invited Paper)
  • Reusing NoC-Infrastructure for Test Data Compression
    2010 V. Fröse, R. Ibers, S. Hellebrand
    Proceedings IEEE VLSI Test Symposium (VTS'10), Santa Cruz, CA, USA, April 2010, pp. 227-231
  • Are Robust Circuits Really Robust?
    2009 S. Hellebrand, M. Hunger
    Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, IL, USA, October 2009, p. 77 (Invited Talk)
  • Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
    2009 M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker
    Proceedings 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Stuttgart, September, 2009
  • ATPG-Based Grading of Strong Fault-Secureness
    2009 M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker
    IEEE International On-Line Testing Symposium 2009 (IOLTS'09), Sesimbra-Lisbon, Portugal, June, 2009
  • Modularer Selbsttest und optimierte Reparaturanalyse
    2008 P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand
    Proceedings 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Ingolstadt, September 2008
  • Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
    2008 M. Hunger, S. Hellebrand
    Proceedings 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Ingolstadt, September 2008
  • A Modular Memory BIST for Optimized Memory Repair
    2008 P. Öhler, A. Bosio, G. Di Natale, S. Hellebrand
    IEEE International On-Line Testing Symposium 2008 (IOLTS'08), Rhodos, Greece, July, 2008 (Poster)
  • Verification and Analysis of Self-Checking Properties through ATPG
    2008 M. Hunger, S. Hellebrand
    IEEE International On-Line Testing Symposium 2008 (IOLTS'08), Rhodos, Greece, July, 2008
  • Signature Rollback - A Technique for Testing Robust Circuits
    2008 U. Amgalan, C. Hachmann, S. Hellebrand, H. Wunderlich
    Proceedings IEEE VLSI Test Symposium (VTS’08), San Diego, CA, USA, May, 2008, pp. 125-130
  • Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007
  • A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Proceedings 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 2007, pp. 50-58
  • An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
    2007 P. Öhler, S. Hellebrand, H. Wunderlich
    Proceedings 12th IEEE European Test Symposium, Freiburg, Germany, pp.91-96, May 2007
  • A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
    2007 M. Ali, M. Welzl, S. Hessler, S. Hellebrand
    Proceedings 4th International Conference on Information Technology: New Generations (ITNG'07), Las Vegas, Nevada, USA, April 2007, pp. 1027-1032
  • Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
    2007 P. Öhler, S. Hellebrand, H. Wunderlich
    Proceedings 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, pp. 185-190, April 2007
  • Test und Zuverlässigkeit nanoelektronischer Systeme
    2007 B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich
    Proceedings 1. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Munich, March 2007
  • Self-checking booth-3 multiplier
    2006 M. Hunger, D. Marienfeld, M. Gössel
    1st. International Conference for Young Researchers in Computer Science, Control, Electrical Engineering and Telecommunications Zielona Góra 2006 (Poster)
  • Considerations for Fault-Tolerant Networks on Chips
    2005 M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand
    Proceedings International Conference on Microelectronics (ICM'05), Islamabad, Pakistan, December 2005
  • A Dynamic Routing Mechanism for Network on Chip
    2005 M. Ali, M. Welzl, S. Hellebrand
    Proceedings 23rd NORCHIP Conference, Oulu Finland, November 2005, pp. 70-73
  • Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
    2005 P. Öhler, S. Hellebrand
    Proceedings 10th IEEE European Test Symposium (ETS'05), Tallinn, Estonia, pp. 148-153, May 2005
  • Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
    2004 A. Wuertenberger, C. Tautermann, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'04), Charlotte, NC, USA, pp. 926-935, October 2004
  • Sensor Networks with more Features using less Hardware
    2004 M. Liu Jing, S. Rührup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann
    GOR/NGB Conference Tilburg 2004
  • A Hybrid Coding Strategy for Optimized Test Data Compression
    2003 A. Wuertenberger, C. Tautermann, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'03), Charlotte, NC, USA, pp. 451-459, September 30 - October 2, 2003
  • Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    2001 H. Liang, S. Hellebrand, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'01), Baltimore, MD, USA, pp. 894-902, November 2001
  • A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    2000 S. Hellebrand, H. Liang, H. Wunderlich
    Proceedings IEEE International Test Conference (ITC'00), Atlantic City, NJ, USA, pp. 778-784, October 2000
  • Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
    1999 V. Yarmolik, I. Bykov, S. Hellebrand, H. Wunderlich
    Proceedings Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, September 15-17, 1999
  • Error Detecting Refreshment for Embedded DRAMs
    1999 S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik
    Proceedings 17th IEEE VLSI Test Symposium, Dana Point, CA, USA, pp. 384-390, April 25-29, 1999
  • Symmetric Transparent BIST for RAMs
    1999 S. Hellebrand, H. Wunderlich, V. Yarmolik
    Proceedings Design, Automation and Test in Europe, DATE'99, Munich, Germany, pp. 702-707, March 9-12, 1999
  • New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
    1998 V. Yarmolik, Y. Klimets, S. Hellebrand, H. Wunderlich
    Proceedings Design & Diagnostics of Eletronic Circuits & Systems, Szczyrk, Poland, pp. 27-33, September 1998
  • Fast Self-Recovering Controllers
    1998 A. Hertwig, S. Hellebrand, H. Wunderlich
    Proceedings 16th IEEE VLSI Test Symposium (VTS'98), Monterey, CA, April 1998, pp. 296-302
  • Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
    1998 S. Hellebrand, H. Wunderlich, V. Yarmolik
    Proceedings Design Automation and Test in Europe, DATE'98, Paris, France, February 1998, pp. 173-179
  • STARBIST: Scan Autocorrelated Random Pattern Generation
    1997 K. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski
    Proc. ACM/IEEE Design Automation Conference, Anaheim, CA, June 1997
  • Mixed-Mode BIST Using Embedded Processors
    1996 S. Hellebrand, H. Wunderlich, A. Hertwig
    Proceedings IEEE International Test Conference, Washington, DC, 1996, pp. 195-204
  • Pattern Generation for a Deterministic BIST Scheme
    1995 S. Hellebrand, B. Reeb, S. Tarnick, H. Wunderlich
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD'95), San Jose, CA, November 1995, pp. 88-94
  • An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
    1994 S. Hellebrand, H. Wunderlich
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD 94), San Jose, CA, November 1994, pp. 110-116
  • Synthese schneller selbsttestbarer Steuerwerke
    1994 S. Hellebrand, H. Wunderlich
    Tagungsband der GI/GME/ITG-Fachtagung & Rechnergestützer Entwurf und Archtektur mikroelektronischer Systeme, Oberwiesenthal, Mai, 1994 (Informatik Xpress 4, TU Chemnitz Zwickau), pp. 3-11
  • Synthesis of Self-Testable Controllers
    1994 S. Hellebrand, H. Wunderlich
    Proceedings European Design Automation Conference (EDAC/ETC/EuroAsic), Paris, France, March 1994, pp. 580-585
  • An Efficient BIST Scheme Based on Resseding of Multiple Polynomial Linear Feedback Shift Registers
    1993 S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick
    Proceedings ACM/IEEE International Conference on Computer-Aided Design (ICCAD'93)
  • Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    1992 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    Proceedings IEEE International Test Conference (ITC'92), Baltimore, MD, 1992, pp. 120-129
  • Generating Pseudo-Exhaustive Vectors for External Testing
    1990 S. Hellebrand, H. Wunderlich, O. Haberl
    Proceedings IEEE International Test Conference (ITC'90), Washington, DC, 1990, pp. 670-679
  • Tools and Devices Supporting the Pseudo-Exhaustive Test
    1989 S. Hellebrand, H. Wunderlich
    Proceedings 1st European Design Automation Conference, EDAC, Glasgow, UK, 1990, pp. 13-17
  • The Pseudo-Exhaustive Test of Sequential Circuits
    1989 H. Wunderlich, S. Hellebrand
    Proceedings IEEE International Test Conference (ITC'89), Washington, DC, 1989, pp. 19-27
  • Automatisierung des Entwurfs vollständig testbarer Schaltungen
    1988 S. Hellebrand, H. Wunderlich
    Proceedings GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer-Verlag, pp. 145-159
  • Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
    1988 H. Wunderlich, S. Hellebrand
    Proceedings 18th International Symposium on Fault-Tolerant Computing, FTCS-18, Tokyo 1988, pp. 36-45
  • Intergrated Tools for Automatic Design for Testability
    1987 D. Schmid, H. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann
    In: Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, 1988, pp. 233-258

Zeitschriften

  • A High Performance SEU Tolerant Latch
    2015 Z. Huang, H. Liang, S. Hellebrand
    Journal of Electronic Testing - Theory and Applications (JETTA), July 2015
  • Adaptive Bayesian Diagnosis of Intermittent Faults
    2014 L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), October 2014, Volume 30, Issue 5, pp 527-540
  • SAT-Based ATPG beyond Stuck-at Fault Testing
    2014 S. Hellebrand, H. Wunderlich
    DeGruyter Journal on Information Technology (it), July 2014, Vol. 56 No. 4, pp. 165-172
  • Signature rollback with extreme compaction - a technique for testing robust VLSI circuits with reduced hardware overhead
    2014 T. Indlekofer
    ANNALES Universitatis Scientiarum Budapestinensis de Rolando Eötvös Nominatae, Vol. 30, pp. 161-180, 2013
  • Variation-Aware Fault Modeling
    2011 F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H. Wunderlich
    SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, Vol. 54, No. 4, pp. 1813-1826
  • New Self-Checking Booth Multipliers
    2008 M. Hunger, D. Marienfeld
    International Journal of Applied Mathematics and Computer Science Vol. 18, No. 3, 2008, DOI: 10.2478/v10006-008-0029-4
  • Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
    2007 S. Hellebrand, C. Zoellin, H. Wunderlich, S. Ludwig, T. Coym, B. Straube
    Informacije MIDEM, Vol. 37, No. 4(124), Ljubljana, December 2007, pp. 212-219 (invited paper)
  • An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip
    2007 M. Ali, S. Hessler, M. Welzl, S. Hellebrand
    International Journal on High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 113-123
  • DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
    2006 B. Becker, I. Polian, S. Hellebrand, B. Straube, H. Wunderlich
    it - Information Technology, Vol. 48, No. 5, pp. 305-311, Oktober 2006
  • Efficient Online and Offline Testing of Embedded DRAMs
    2002 S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, V. Yarmolik
    IEEE Transactions on Computers, Vol. 51, No. 7, July 2002, pp. 801-809
  • Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    2002 S. Hellebrand, H. Liang, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168
  • A mixed-mode BIST scheme based on folding compression
    2002 H. Liang, S. Hellebrand, H. Wunderlich
    Journal of Computer Science and Technology, March 2002, Vol. 17, issue 2, pp. 203-212
  • A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    2001 S. Hellebrand, H. Liang, H. Wunderlich
    Journal of Electronic Testing - Theory and Applications, JETTA, Vol. 17, No. 3/4, June/August 2001, pp. 341-349
  • Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
    1998 S. Hellebrand, A. Hertwig, H. Wunderlich
    IEEE Design and Test, Vol. 15, No. 4, October-December 1998, pp. 36-41
  • Mixed-Mode BIST Using Embedded Processors
    1998 S. Hellebrand, H. Wunderlich, A. Hertwig
    Journal of Electronic Testing Theory and Applications - JETTA, Vol. 12, Nos. 1/2, February/April 1998, pp. 127-138
  • Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
    1995 S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois
    IEEE Transactions on Computers, Vol. 44, No. 2, February 1995, pp 223-233
  • The Pseudo-Exhaustive Test of Sequential Circuits
    1991 H. Wunderlich, S. Hellebrand
    IEEE Transactions on Computer-Aided Design of Intergated Circuits and Systems, Vol. 11, No. 1, January 1992, pp. 26-33

Buchkapitel

  • Mixed-Mode BIST Using Embedded Processors
    1997 S. Hellebrand, H. Wunderlich, A. Hertwig
    In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998

Bücher

  • Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
    1998 S. Hellebrand
    Hamburg: Verlag Dr. Kovac, 1999
  • Synthese vollständig testbarer Schaltungen
    1990 S. Hellebrand
    Fortschritt-Berichte VDI, Reihe 10, Nr. 177; Verlag Düsseldorf: VDI Verlag, 1991

Workshop Beiträge

  • X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
    2017 M. Kampmann, S. Hellebrand
    29. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'17). Lübeck, 5. - 7. März 2017
  • Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
    2015 S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H. Wunderlich
    27. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, 1. - 3. März 2015
  • Adaptive Test and Diagnosis of Intermittent Faults
    2013 A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H. Wunderlich
    Latin American Test Workshop, Cordoba, Argentina, April 2013
  • Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
    2012 A. Cook, S. Hellebrand, H. Wunderlich
    24. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'12), Cottbus, 26. - 28. Februar 2012
  • Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
    2010 V. Fröse, R. Ibers, S. Hellebrand
    22. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'10), Paderborn, 28. Februar - 2. März 2010
  • Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
    2008 U. Amgalan, C. Hachmann, S. Hellebrand, H. Wunderlich
    20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Wien, Österreich, März 2008
  • Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
    2008 T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H. Wunderlich, C. Zoellin
    20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Wien, Österreich, März 2008 (Poster)
  • Reliable nanoscale systems - challenges and strategies for on- and offline testing
    2007 S. Hellebrand
    5th IEEE East-West Design & Test Symposium, September 2007, Yerevan, Armenia (Invited Talk)
  • An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
    2007 M. Ali, M. Welzl, S. Hessler, S. Hellebrand
    DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, April 2007 (Poster)
  • An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
    2007 P. Öhler, S. Hellebrand, H. Wunderlich
    17th GI/ITG/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Erlangen, Germany, March 2007
  • A Low Power Design for Embedded DRAMs with Online Consistency Checking
    2005 P. Öhler, S. Hellebrand
    Kleinheubachertagung 2005, Miltenberg, Germany
  • Power Consumption versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
    2005 P. Öhler, S. Hellebrand
    117th GI/ITG/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, March 2005
  • Dynamic Routing: A Prerequisite for Reliable NoCs
    2005 M. Ali, M. Welzl, S. Hellebrand
    17th GI/ITG/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Innsbruck, Austria, March 2005
  • Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
    2004 S. Hellebrand, A. Wuertenberger, C. Tautermann
    9th IEEE European Test Symposium, Ajaccio, Corsica, France, May 22-26, 2004
  • Alternating Run-Length Coding: A Technique for Improved Test Data Compression
    2002 S. Hellebrand, A. Wuertenberger
    IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, October 2002
  • Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
    2001 H. Liang, S. Hellebrand, H. Wunderlich
    IEEE European Test Workshop, Stockholm, Sweden, May 2001
  • A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
    2000 S. Hellebrand, H. Liang, H. Wunderlich
    IEEE European Test Workshop, Cascais, Portugal, May 2000
  • Exploiting Symmetries to Speed Up Transparent BIST
    1999 S. Hellebrand, H. Wunderlich, V. Yarmolik
    11th GI/ITG/GMM/IEEE Workshop
  • Efficient Consistency Checking for Embedded Memories
    1998 V. Yarmolik, S. Hellebrand, H. Wunderlich
    5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, March 1998
  • Efficient Consistency Checking for Embedded Memories
    1998 V. Yarmolik, S. Hellebrand, H. Wunderlich
    10th GI/ITG/GMM/IEEE Workshop
  • Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
    1997 A. Hertwig, S. Hellebrand, H. Wunderlich
    3rd IEEE International On-Line Testing Workshop, Crete, Greece, July 1997
  • STARBIST: Scan Autocorrelated Random Pattern Generation
    1997 K. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska
    4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, May 1997
  • Mixed-Mode BIST Using Embedded Processors
    1996 S. Hellebrand, H. Wunderlich, A. Hertwig
    2nd IEEE International On-Line Testing Workshop. Biarritz, France, July 1996
  • Using Embedded Processors for BIST
    1996 S. Hellebrand, H. Wunderlich
    3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, May 1996
  • Pattern Generation for a Deterministic BIST Scheme
    1995 S. Hellebrand, B. Reeb, S. Tarnick, H. Wunderlich
    2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, May 1995
  • Synthesis for Testability - the ARCHIMEDES Approach
    1994 S. Hellebrand, J. Teixeira, H. Wunderlich
    1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, May 1994
  • Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
    1994 S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick
    6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Vaals, March 1994
  • Ein Verfahren zur testfreundlichen Steuerwerkssynthese
    1994 S. Hellebrand, H. Wunderlich
    6th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Vaals, March 1994
  • Synthesis of Self-Testable Controllers
    1993 S. Hellebrand, H. Wunderlich
    ARCHIMEDES Open Workshop on "Synthesis - Architectural Testability Support", Montpellier, France, July 1993
  • Effiziente Erzeugung deterministischer Muster im Selbsttest
    1993 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    5th ITG/GI/GME Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Holzhau, March 1993
  • Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
    1992 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    Workshop on New Directions for Testing, Montreal, Canada, May 1992
  • Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
    1992 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    IEEE Design for Testability Workshop, Vail, CO, April 1992
  • Generating Pseudo-Exhaustive Vectors for External Testing
    1990 S. Hellebrand, H. Wunderlich, O. Haberl
    IEEE Design for Testability Workshop, Vail, CO, April 1990

Report

  • Test und Synthese schneller eingebetteter Systeme
    1998 S. Hellebrand, H. Wunderlich
    Arbeitsbericht über das DFG-Projekt Wu 245/1-1, Abteilung Rechnerarchitektur, Institut für Informatik, Universität Stuttgart, Februar 1998
  • Synthesis Procedures for Self-Testable Controllers
    1995 S. Hellebrand, H. Wunderlich
    Deliverable Report A1/SIE/m36, ESPRIT Project 7107 ARCHIMEDES, Institute of Computer Structures, University of Siegen, September 1995
  • Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
    1995 S. Hellebrand, H. Wunderlich, F. Goncalves, J. Teixeira
    Deliverable Report B4.2/SIE/m36, ESPRIT Project 7107 ARCHIMEDED, Institute of Computer Structures, University of Siegen, September 1995
  • Partitioning of CMOS-Circuits for
    1995 S. Hellebrand, M. Herzog, H. Wunderlich
    Deliverable Report C2.4/SIE/m36, ESPRIT Project 7107 ARCHIMEDES, Institute of Computer Structures, University of Siegen, September 1995
  • Synthesis for Off-line Testability
    1993 S. Hellebrand, A. Jürgensen, H. Wunderlich
    Deliverable Report A1/SIE/m18, ESPRIT Project 7107 ARCHIMEDES, Institute of Computer Structures, University of Siegen, January 1994
  • Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
    1993 S. Hellebrand, A. Jürgensen, A. Ströle, H. Wunderlich
    Deliverable Report A4/SIE/m18, ESPRIT Project 7107 ARCHIMEDES, Institute of Computer Structures, University of Siegen, January 1994
  • Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
    1992 S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois
    TIM3 Research Report, TIM3/IMAG, Institut National Polytechnique de Grenoble, Grenoble, France, March 1992
  • Deformation dicker Punkte und Netze von Quadriken
    1985 S. Hellebrand
    Regensburger Mathematische Schriften 9, Fakultät für Mathematik der Universität Regensburg, Regensburg 1986

Verschiedenes

  • Nano-electronic Systems
    2010 S. Hellebrand
    Editorial, it 4/2010, pp. 179-180
  • Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
    2007 S. Hellebrand
    ForschungsForum Paderborn, 10. Ausgabe, 2007
  • Im Westen viel Neues - Informatik an der Universität Innsbruck
    2004 R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer
    OCG Journal, 29/1/2004, pp. 28-29
  • Experience from Teaching Software Development in a Java Environment
    2003 R. Breu, S. Hellebrand, M. Welzl
    Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, July 2003, Tunis, Tunisia
  • Hardwarepraktikum im Diplomstudiengang Informatik
    1999 S. Hellebrand, H. Wunderlich
    Handbuch Lehre, Berlin, Raabe Verlag, 2000
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Gruppenleitung

Sybille Hellebrand

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Prof.
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