Vergleich und Entwicklung eines X-Reduzierenden Kompaktierungsverfahrens für Faster-than-At-Speed Test (FAST)
Studierender: Mohammad Urf Maaz
Recent advances in fabrication and production of devices have also introduced smaller delay defect sizes. Hidden delay defects are of particular interest as they are not large enough to cause timing failure under normal condition. Small delay defects would not be of much concern as they do not introduce significant delays at normal frequency of operation. However, hidden delay defects are indicative of imperfections occurring in device. These imperfections can lead to early life failures in many devices and therefore detection of such defects is crucial.
A solution to this is performing Faster-than-At-Speed Testing (FAST). In FAST the test is run at significantly higher frequencies than normal operation. At these high frequencies, these delay defects are detected. However, working at higher frequencies comes with its own complications. Since the test responses are gathered at significantly higher frequencies, there are many intermediate value arriving particularly from longer paths. This means that the number of unknowns (X) increase in FAST. These X’s arrive in the test responses and present a series of issues to evaluating results.
There are several techniques to handle these unknowns such that the test results can be somewhat effectively evaluated. Few researchers have proposed modifying the CUT however that is not very practical for general purpose. Instead, more efficient approaches target not the elimination of X’s from the circuit, but the handling of X’s in the outputs. Bawa et al. present X-Canceling MISR techniques with partial masking in X-chains as and effective approach of removing the effect of several unknown values while losing only a few of the known values. The X-Canceling MISR proposed earlier by Touba is effective for small densities of X’s while Bawa’s improved approach of partial masking handles the higher densities more effectively. As a result, we have fewer test vectors and better compression of test data. However, this is still not FAST-ready.
Rajski et al. present convolution compaction of test responses as an approach to handling X’s. Datta and Touba present an X-stacking method to reduce the cost of handling the unknown values in test responses. There are several other methods similar and different from the aforementioned techniques. This thesis plans on extensive research on the mentioned approaches for reduction of X’s in output responses for FAST. In this first stage of the thesis, contemporary approaches will be studied and investigated. These will provide a good basis. Literature review will also involve in-depth understanding of FAST. This would be followed by implementing few of the suitable techniques and comparing the results of each. This study would provide a valuable insight to the superiority of each method and the suitability for the high X density in FAST responses. Each important study must be followed with implementation in the existing framework using C++ and comparison with the other contemporary methods. Finally documentation of the thesis will be compiled and presented.
In order to test and verify the implemented techniques some parameters need to be set and investigated. Since the approaches differ significantly from each other, some evaluating ground must be established.
The first trivial aspect is the pure reduction or removal of unknowns. The implemented work will serve as a block that receives outputs with high percentages of X’s and in turn reduces them to create an output stream that contains a tolerable number of X’s. This output stream may be fed to an X-Canceling MISR, which would work efficiently with the low number of X’s. The X-reduction must then be measured across the block to be implemented i.e. number of X’s from the incoming stream to the reduced number of X’s in the stream fed to the X-Canceling MISR.
Next a similar aspect is to evaluate the fault coverage achieved through the masking or reduction procedure. Having a high fault coverage is the ultimate goal and therefore evaluating the comparative fault coverage for the implemented scheme serves as a good basis for evaluation.
Another important aspect that can be evaluated is the hardware overhead that is dedicated for the implemented scheme. While the scheme must be effective in itself it must also be feasible. For example, one of the evaluating parameters in the partial masking techniques proposed by Bawa was the total number of control bits required. In their approach, number of X-chains was also varied in order to see the effect on the number of control bits required. In the X-Stacking approach by Datta and Touba, additional test vectors were required to achieve 100% coverage and their relative percentage increase investigated. Similarly for other approaches, having a feasible hardware overhead would be beneficial and therefore can serve as an additional evaluating parameter.
The implemented schemes shall first be tested on simpler circuits before moving to industrial boards if possible. Also tweaking with the frequency of testing can also give a good idea of the optimum frequency range i.e. where maximum number of faults are covered with the minimum number of X’s produced. These are some of the potential evaluating aspects that can be used in order to compare the contemporary schemes.