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Faster-than-at-Speed Logic BIST

Studierender: Ratna Kumar Gari

State of the art manufaction processes and technologies allow for much tighter integration densities on the chips. This has the advantages of reduced power dissipation and increased operating frequencies, but has the drawback of chips being very sensitive even to small, natural process variations. Furthermore, Early Life Failures (ELFs) are becoming a dominant problem in applications with high reliability. One indicator for ELFs is the Small Delay Fault (SDF). These faults can be hidden when the test is performed at-speed. To overcome this problem, Faster-than-At-Speed Test (FAST) was introduced. Essentially, in FAST the test is performed while overclocking the chip.

FAST can also be implemented as a Built-in Self-Test (BIST). The Computer Engineering research group published several conference papers about FAST-BIST in cooperation with the university of Stuttgart. However, all the approaches use deterministic test patterns, which need to be stored in an on-chip memory. For BIST, an attractive method of generating test patterns with low hardware overhead is to use a Linear Feedback Shift Register (LFSR). It produces a stream of pseudo-random test patterns which are applied to the chip. In the industry, this practice is commonly called Logic Built-in Self-Test (LBIST).

Problem description:

In this master’s thesis, the usability of LFSRs should be analyzed with respect to FAST. The challenge here is to find maximum-length sequences in the stream of pseudo-random patterns such that each sequence can be applied to the chip at a single test frequency. Ultimately, the fault coverage should be maximized with this technique while at the same time reducing the required hardware overhead for FAST-BIST.

Key aspects:

  • Analysis of deterministic test patterns to find "strong" patterns
  • Analysis of LFSR output streams
  • Implementation of an algorithm to find sequences in the stream
  • Experimental case study to validate the results

Prerequesites:

  • Knowledge about VLSI testing, BIST and especially LFSRs
  • Programming skills, preferrably in C++
  • Motivation to work on a current research topic

Bibliography:

  • S. Hellebrand et al. FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. Proceedings of the IEEE International Test Conference (ITC), 2014. pp 1-8
  • M. Kampmann et al. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Proceedings of the IEEE Asian Test Symposium (ATS), 2015, pp 109-114

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