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The Computer Engineering Group focuses on research acitivities in the area of test and diagnosis of nanoscale "systems-on-a-chip" (SoCs) as well as on fault tolerant design and the verification of fault tolerance properties. Nanoscale manufacturing processes are characterized by an increasing vulnerability to defects and by increasing parameter variations both among and inside chips.


News

Presentation in our research seminar

On Thursday, May 3rd, Moritz Schniedermann will give an intermediate talk about his masters thesis SAT-basierte Testmustererzeugung für Verzögerungsfehler (in German). The talk will be held at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join the talk!

Interim Talk

On Wednesdey, April 18th at 9.30am Manuel Boschman will give an interim talk on his bacheor thesis

Implementierung und Analyse eines rekonfigurierbaren X-toleranten Signaturregisters

The talk will take place in room P1.6.16.2

Results for exam on "Introduction to Algorithms"

The results of the exam "Introduction to Algorithms" from March 26 are now published in the display case in front of P1.6.08.

The exam review will be held on Thursday, April 12, from 2pm-3pm in P1.6.17.1.

Preliminary course meeting for summer term 2018

On Tuesday, April 10th, the preliminary course meeting for seminars in this summer term takes place. It is being held at 2pm in our seminar room (P1.6.17.1).

Further information can be found in the corresponding  PANDA course.

Conference-Paper accepted

The Conference-Paper of Alexander Sprenger and Sybille Hellebrand with the Topic:

Tuning Stochastic Space Compaction to Faster-than-At-Speed Test

was accepted at "21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)". Alexander Sprenger willl present the work in Budapest on April 25th.

 

Head

Sybille Hellebrand

Computer Engeneering Group

Head of Group

Prof.
Phone:
(+49) 5251 60-4259
Fax:
(+49) 5251 60-4221
Office:
P1.6.08.1 (Map)

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