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The Computer Engineering Group focuses on research acitivities in the area of test and diagnosis of nanoscale "systems-on-a-chip" (SoCs) as well as on fault tolerant design and the verification of fault tolerance properties. Nanoscale manufacturing processes are characterized by an increasing vulnerability to defects and by increasing parameter variations both among and inside chips.


News

Submission to Workshop Accepted

Matthias Kampmann and Sybille Hellebrand successfully submitted their contribution Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test to the IEEE "Workshop on RTL and High-Level Testing" (WRTLT). Matthias Kampmann will present the paper in October in China.

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Journal Paper Accepted

Matthias Kampmann and Sybille Hellebrand successfully submitted their article Built-in Test for Hidden Delay Faults, created in cooperation with Michael Kochte, Chang Liu, Eric Schneider and Hans-Joachim Wunderlich from the University of Stuttgart, to the IEEE journal "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems". The article will be published soon.

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Presentation on August 1st

Manuel Boschmann will give his final talk on his bachelor thesis with the title:

Implementierung und Analyse eines rekonfigurierbaren X-toleranten Signaturregisters

on Wednesday, August 1st at 2pm in room P1.6.17.1. Everyone interested is invited to participate.

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Presentation in the research seminar

On Thursday, July 5th, Moritz Schniedermann will give his final presentation about his Masters Thesis SAT-basierte Testmustererzeugung für Verzögerungsfehler (in German). The talk will take place at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

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Presentations in the research seminar

On Thursday, June 6th, the following talks will be given as part of our research seminar:

  • Mehak Aftab will give her introductory talk about her Masters Thesis X-Aware Pattern Selection for Faster-than-at-Speed Test
  • Viktor Tran and Jan Dennis Reimer will give their final presentation of their group project Fehleremulation für den Software-basierten Selbsttest - Eine experimentelle Evaluation für den Leon3-Prozessor

The talks will start at 9:30am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

open Thesis
  • Currently there are no open thesis topics. Please wirte an application including a transcript of grades to our staff members if you are interested in writing a thesis at our research group!.
Head

Sybille Hellebrand

Computer Engeneering Group

Head of Group

Prof.
Phone:
(+49) 5251 60-4259
Fax:
(+49) 5251 60-4221
Office:
P1.6.08.1 (Map)

to Person

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