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The Computer Engineering Group focuses on research acitivities in the area of test and diagnosis of nanoscale "systems-on-a-chip" (SoCs) as well as on fault tolerant design and the verification of fault tolerance properties. Nanoscale manufacturing processes are characterized by an increasing vulnerability to defects and by increasing parameter variations both among and inside chips.


News

Journal paper submission accepted

Matthias Kampmann and Sybille Hellebrand got their submission "Design for Small Delay Test - A Simulation Study" to the journal "Microelectronics Reliability", published by Elsevier, accepted. In their submission, the authors further analyze the proposed "Design-for-FAST" architecture, which they previously published in the award-winning paper "Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test". They integrated the approach into an industrial synthesis workflow and performed an extensive simulation study on circuits synthesized with this approach. They show the advantages and disadvantages of "Design-for-FAST", when it is compared to a standard synthesis process.

Presentations in our research seminar

On Thursday, December 7, the following talks will be given as part of our research seminar:

  • Jan Dennis Reimer will talk about his work as a student assistant in our group
  • Moritz Schniedermann will give an intermediate talk about the state of his masters thesis SAT-basierte Testmustererzeugung für Verzögerungsfehler

The talks will start at 11am in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join!

Presentations in the research group

The following presentations will be given in soon in our research group:

  • October 12, 9:30am: Moritz Schniedermann will give a first talk about his Masters thesis.
  • October 12, 10am: Viktor Bakhmetiev will talk about his work done as an SHK in our research group.
  • October 19, 9:30am: Thomas Mertens will give an intermediate talk about his Bachelors thesis, titled "Experimenteller Vergleich von Kompaktierungsstrategien für den eingebetteten Hochgeschwindigkeitstest"
  • October 19, 10am: Roman Borisenko will give the final presentation on his Bachelor's thesis, titled "Direct Diagnosis for FAST"

The presentations will be held in our seminar room (P1.6.17.1). Everyone interested is cordially invited to join the talks!

Presentation in our research seminar

On Tuesday, July 11, Prof. Wenjing Rao from the University of Illinois, Chicago (UIC), USA, will give a guest talk as part of our research seminar. The title of the talk is

Guaranteed k-Fault Tolerance in Scalable Systems

The talk will be given at 10am in the room P1.3.01. Everyone interested is cordially invited to join!

Read More

Best Paper Award conferred to Matthias Kampmann and Sybille Hellebrand

At the IEEE DDECS 2017 in Dresden, the Best Paper Award in the test field was conferred to Matthias Kampmann and Sybille Hellebrand for their excellent submission. The award was given for the paper "Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test".

 

open Thesis
  • Currently there are no open thesis topics. Please wirte an application including a transcript of grades to our staff members if you are interested in writing a thesis at our research group!.
Head

Sybille Hellebrand

Computer Engeneering Group

Head of Group

Prof.
Phone:
(+49) 5251 60-4259
Fax:
(+49) 5251 60-4221
Office:
P1.6.08.1 (Map)

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